FIG. 1 illustrates a high-voltage, n-channel, Metal-Oxide-Semiconductor, Field-Effect Transistor 100 in the prior art. The transistor 100 is formed on a p− substrate 120, which can be formed from silicon. Preferably the substrate 120 is doped relatively lightly (1015 atoms per centimeter3) with a p-type material, such as boron ions.
A p-well 102 and an n-well 110 are diffused or implanted into the p− substrate 120. The p-well 102 appears twice in FIG. 1, but that is only because it surrounds n-well 110, and FIG. 1 is taken at a cross section that shows the p-well 102 in two places. The n-well drain 110 and the p-well 102 are typically doped on the order of 1017 atoms per centimeter3.
The transistor 100 has terminals that are provided for as follows. Contained within the n-well 110 is an n+ region 112 (“n+ Tap”), which is suitable for receiving a drain contact. The p-well 102 also has a p+ region 116 (“p+ Tap”) that provides for an ohmic-contact for the body of the p− substrate 120 via the p-well 102. An n+ well 114 is located at least in part of the p-well 102, which is adapted to receive a source contact. The n+ well 114 contains an abundance of n-type material, such as arsenic ions. In fact, the plus (+) sign next to either the letter “n” or the letter “p” indicates an overabundant doping of a particular n-type material or p-type material, which can be of the order of 1020 atoms per centimeter3.
A thin gate dielectric layer 118 is disposed or grown onto the p− substrate 120. The layer 118 can be formed integrally with a thick field oxide (“FOX”) layer 108A, which operates as a stop.
An n+ polysilicon gate 104 is formed onto gate layer 118. The gate 104 is suitable for receiving a gate contact (not shown). Sidewall spacers 106A, 106B are formed on either side of the gate 104.
Accordingly, an active region for the transistor 100 is defined under the gate 104. A channel for the transistor 100 is defined in the active region, within the p-well 102, between the n+ well 114 and the n-well 110. The thick FOX stop 108A, and another FOX stop 108B act as shallow trend isolation (“STI”) to prevent inadvertent channel formation outside of the active region of the transistor 100.
So, when a positive voltage is applied to the n+ polysilicon gate 104 relative to the p-well 102, positive charges are, in effect, deposited on it. In response, negative charges are induced in the underlying p-well 102 by the formation of a depletion region and a thin inversion surface region near the gate dielectric layer containing mobile electrons, resulting in conductible current. These induced mobile electrons form the channel of the transistor 100, and allow current to flow between the n-well 110 and the n+ source 114, in a direction that depends on the sizes of the biasing voltages.
In the transistor 100, no current flows from the n-well 110 to the n+ source 114 without a conducting n-channel between them, since the drain-body-source combination includes oppositely directed p-n junctions in series, which can be likened to diodes whose cathodes are coupled together.
Indeed, in the transistor 100, a natural p-n junction is created between the p-well 102 and the adjacent n-well 110. It should be noted that the p-well 102 and the adjacent n-well 110 have doping of density that is intermediate between the lightly doped substrate 120 and the heavily doped contact areas, namely the n+ region 112, the n+ source 114, and p+ region 116.
In conventional MOS transistors, the n+ region 112 could act as the drain without providing the n-well 110. This, however, created significant problems when such transistors are used in high-voltage applications. For example, suppose a high voltage, such as 10V or more, were applied to the n+ region 112 without the n-well 110. Such a high voltage can cause a breakdown of the operative p-n junction, allowing current to undesirably flow from the n+ region 112 to the p-well 102, instead of to the n+ source 114. The transistor 100 prevents such a breakdown because the n-well 110 places the natural p-n junction-well away from the n+ region 112, which is therefore free to be interfaced to high voltages.
While this solution worked, it was discovered by the inventors that another problem appeared. When a sufficient voltage is introduced at the gate 104, breakdown of the natural p-n junction may occur. In fact, the voltage applied at the n+ polysilicon gate 104 affects the breakdown voltage of the natural p-n junction formed by the n-well 110 and the p-well 102. The breakdown occurs because there is an overlap, where the n+ polysilicon gate 104 extends over a portion of the n-well 110. The breakdown causes current to conduct undesirably from the n-well 110 to the p-substrate 120 instead of toward the n+ source 114.
Without a resolution to the problem of undesired breakdown of the transistor 100, users may eventually no longer trust the reliability of computing devices built using transistors such as transistor 100. Thus, there is a need for a new transistor and method for inhibiting or alleviating the breakdown of p-n junctions while avoiding or reducing other problems associated with existing transistors.